 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| adis16250/ adis16255 programmable low power gyroscope preliminary technical data adis16260/adis16265 features yaw rate gyroscope with range scaling 80/sec, 160/sec, and 320/sec settings spi?-compatible serial interface calibrated sensitivity and bias adis16260: +25c adis16265: ?40c to +85c digital temperature sensor output in-system, auto-zero for bias drift calibration digitally controlled sample rate, up to 2048sps digitally controlled frequency response 50/300hz sensor bandwidth selection programmable bartlett window fir filter dual alarm settings with configurable operation embedded integration for short-term angle estimates digitally activated self-test digitally activated low power mode interrupt-driven wake-up auxiliary 12-bit adc input and 12-bit dac output auxiliary digital input/output single-supply operation: 4.75 v to 5.25 v 2000 g powered shock survivability general description the adis16260/adis16265 are complete angular rate meas- urement systems available in a single compact package enabled by analog devices, inc. i sensor? integration. by enhancing analog devices i mems? sensor technology with an embedded signal processing solution, the adis16260/adis16265 provide factory-calibrated and tunable digital sensor data in a convenient format that can be accessed using a simple spi serial interface. the adis16265 additionally provides an extended temperature calibration. the spi interface provides access to measurements for the gyroscope, temperature, power supply, and one auxiliary analog input. easy access to calibrated digital sensor data provides developers with a system-ready device, reducing development time, cost, and program risk. applications instrumentation control platform control and stabilization motion control and analysis avionics instrumentation navigation image stabilization robotics functional block diagram a ux aux adc dac vref sclk din dout cs rst dio0 dio1 spi port temperature sensor self-test power management auxiliary i/o alarm digital control signal conditioning and conversion calibration and digital processing vcc filt rate com gyroscope sensor 06070-001 figure 1. the device range can be digitally selected from three different settings: 80/sec, 160/sec, and 320/sec. unique charac- teristics of the end system are accommodated easily through several built-in features, including a single-command auto-zero recalibration function, as well as configurable sample rate and frequency response. additional features can be used to further reduce system complexity, including: ? configurable alarm function ? auxiliary 12-bit adc and dac ? two configurable digital i/o ports ? digital self-test function ? digital sensor bandwidth selection system power dissipation can be optimized via the adis16260/ adis16265 power management features, including an interrupt- driven wake-up. the adis16260/adis16265 are available in an 11 mm 11 mm 5.5 mm, laminate-based land grid array (lga) package with a temperature range of ?40c to +85c. rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. tel: 781.329.4700 www.analog.com trademarks and registered trademarks are the property of their respective owners. fax: 781.461.3113 ?2006C2008 analog devices, inc. all rights reserved. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? adis16260/adis16265 preliminary technical data table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 recommended layout ................................................................. 7 typical performance characteristics ............................................. 8 theory of operation ........................................................................ 9 overview ........................................................................................ 9 relative angle estimate ............................................................... 9 revision history 11/08rev. b to rev. c deleted temperature sensor parameter, table 1 .......................... 3 added logic inputs conditions and digital outputs conditions ......................................................................................... 4 3/07rev. a to rev. b changes to table 2 and figure 2 ..................................................... 5 changes to table 8 .......................................................................... 13 changes to table 9 and table 11 ................................................... 14 changes to table 24 ........................................................................ 16 changes to data-ready i/o indicator section ........................... 17 changes to self-test section ......................................................... 17 factory calibration .......................................................................9 auxiliary adc function ..............................................................9 basic operation .............................................................................. 10 serial peripheral interface (spi) ............................................... 10 data output register access .................................................... 11 programming and control ............................................................ 12 control register overview ....................................................... 12 control register structure ........................................................ 12 calibration ................................................................................... 13 global commands ..................................................................... 13 operational control ................................................................... 14 status and diagnostics ............................................................... 16 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 2/07rev. 0 to rev. a added adis16265..............................................................universal changes to table 1 ............................................................................. 3 changes to table 2 ............................................................................. 5 changes to figure 2 ........................................................................... 5 changes to typical performance characteristics .......................... 8 deleted temperature sensor section ........................................... 11 added factory calibration section .............................................. 11 changes to table 7 .......................................................................... 12 changes to table 8 .......................................................................... 13 changes to table 11 ....................................................................... 14 changes to table 19 ....................................................................... 16 changes to flash memory endurance section .......................... 18 changes to ordering guide .......................................................... 20 10/06revision 0 : initial version rev. pra | page 2 of 19 preliminary technical data adis16260/adis16265 specifications t a = ?40c to +85c, v cc = 5.0 v, angular rate = 0/sec, 1 g , 320/sec range setting, unless otherwise noted. table 1. parameter conditions min typ max unit sensitivity 1 initial tolerance temperature coefficient nonlinearity clockwise rotation is positive output 25c, dynamic range = 320/sec 2 25c, dynamic range = 160/sec 25c, dynamic range = 80/sec 25c, dynamic range = 320/sec adis16260 adis16265 best fit straight line 0.07326 0.03663 0.01832 0.2 1 tbd 25 0.1 /sec/lsb /sec/lsb /sec/lsb % ppm/c ppm/c % of fs bias in run bias stability turn-on-to-turn-on bias stability angular random walk temperature coefficient linear acceleration effect voltage sensitivity 25c, 1 25c, 1 25c, 1 adis16260 adis16265 any axis v cc = 4.75 v to 5.25 v 0.007 0.05 2 tbd 0.005 0.2 1.0 /sec /sec /hour /sec/c /sec/c /sec/ g /sec/v noise performance output noise at 25c, 320/sec rang e, no filtering tbd /sec rms at 25c, 160/sec range, 4-tap filter setting tbd /sec rms at 25c, 80/sec range, 16-tap filter setting tbd /sec rms rate noise density at 25c, f = 25 hz, 320/sec range, no filtering 0.05 /sec/hz rms frequency response 3 db bandwidth sens_avg[7] = 1 50 hz sens_avg[7] = 0 300 sensor resonant frequency 14 khz self-test state change for positive stimulus 320/sec dynamic range setting tbd tbd tbd lsb change for negative stimulus internal self-test cycle time 320/sec dynamic range setting tbd tbd tbd 20 lsb ms adc input resolution 12 bits integral nonlinearity 2 lsb differential nonlinearity 1 lsb offset error 4 lsb gain error 2 lsb input range 0 2.5 v input capacitance during acquisition 20 pf on-chip voltage reference 2.5 v accuracy at 25c ?10 +10 mv temperature coefficient 40 ppm/c output impedance 70 rev. pra | page 3 of 19 adis16260/adis16265 preliminary technical data parameter conditions min typ max unit dac output 5 k/100 pf to gnd resolution 12 bits relative accuracy for code 101 to code 4095 4 lsb differential nonlinearity 1 lsb offset error 5 mv gain error 0.5 % output range 0 to 2.5 v output impedance 2 output settling time 10 s logic inputs internal 3.3 v interface input high voltage, v inh 2.0 v input low voltage, v inl 0.8 v for cs signal when used to wa ke up from sleep mode 0.55 v logic 1 input current, i inh logic 0 input current, i inl v ih = 3.3 v v il = 0 v 0.2 10 a all except rst ?40 ?60 a rst 3 ?1 ma input capacitance, c in 10 pf digital outputs output high voltage, v oh output low voltage, v ol internal 3.3 v interface i source = 1.6 ma i sink = 1.6 ma 2.4 0.4 v v sleep timer timeout period 4 0.5 128 sec start-up time initial sleep mode recovery 160 2.5 ms ms flash memory endurance 5 data retention 6 t j = 55c 20,000 20 cycles years conversion rate minimum conversion time 0.488 ms maximum conversion time 7.75 sec maximum throughput rate 2048 sps minimum throughput rate 0.129 sps power supply operating voltage range, v cc 4.75 5.0 5.25 v power supply current normal mode at 25c tbd ma fast mode at 25c tbd ma sleep mode at 25c tbd a 1 adis16265 characterization data represe nts 4 to fall within the 1% limit. 2 the sen sor is capable of 600/sec, but the specifications herein are for 320/sec only. 3 the rst pin has an internal pull-up. 4 guaranteed by design. 5 endurance is qualified as per jedec standard 22 method a117 and measured at ?40c, +25c, +85c, and +125c. 6 retention lifetime equivalent at junction temperature (t j ) 55c, as per jedec standard 22 me thod a117. retention lifetime decr eases with junction temperature. rev. pra | page 4 of 19 preliminary technical data adis16260/adis16265 timing specifications t a = ?40c to +85c, v cc = 5.0 v, unless otherwise noted. table 2. parameter description min 1 typ max 1 unit f sclk fast mode, smpl_prd 0x07 (f s 64 hz) 0.01 2.5 mhz normal mode, smpl_prd 0x08 (f s 56.9 hz) 0.01 1.0 mhz t datarate data rate period, fast mode, smpl_prd 0x07 (f s 64 hz) 32 s data rate period, normal mode, smpl_prd 0x08 (f s 56.9 hz) 42 s t stall stall period, fast mode, smpl_prd 0x07 (f s 64 hz) 9 s stall period, normal mode, smpl_prd 0x08 (f s 56.9 hz) 12 s t cs chip select to clock edge 48.8 ns t dav data output valid after sclk falling edge 2 100 ns t dsu data input setup time before sclk rising edge 24.4 ns t dhd data input hold time after sclk rising edge 48.8 ns t df data output fall time 5 12.5 ns t dr data output rise time 5 12.5 ns t sfs cs high after sclk edge 3 5 ns flash update time (power supply must be within range) 50 ms 1 guaranteed by design; not production tested. 2 the msb presents an exception to this parameter. the msb clocks out on the falling edge of cs . the rest of the dout bits are clocked after the falling edge of sclk and are governed by this specification. 3 this parameter may need to be expanded to allow for proper capture of the lsb. after cs goes high, the dout line goes into a high impedance state. cs sclk t datarate t datastall figure 2. spi chip select timing cs sclk dout din 06070-026 1 2 3 4 5 6 15 16 w/r a5 a4 a3 a2 d2 msb db14 d1 lsb db13 db12 db10 db11 db2 lsb db1 t cs t sfs t dav t dhd t dsu * *not defined 06070-003 figure 3. spi timing (using sp i settings typically identified as phase = 1, polarity = 1) rev. pra | page 5 of 19 adis16260/adis16265 preliminary technical data absolute maximum ratings table 3. parameter acceleration (any axis, unpowered, 0.5 ms) 2000 g acceleration (any axis, powered, 0.5 ms) 2000 g v cc to com ?0.3 v to +6.0 v digital input/output voltage to com ?0.3 v to +5.5 v analog inputs to com ?0.3 v to +3.5 v operating temperature range 1 ?40c to +125c storage temperature range 1 ?65c to +150c rating 1 extended exposure to temperatures outside of the specified temperature range of ?40c to +85c can adversely affect the accuracy of the factory calibration. for best accuracy, store the parts within the specified operating range of ?40c to +85c. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. rateout rate axis +8191 lsb longitudinal axis clockwise rotation 10 C8192 lsb lateral axis 1 5 6 ratein 06070-011 figure 4. rateout level increase with clockwise rotation increase esd caution rev. pra | page 6 of 19 adis16250/ adis16255 preliminary technical data adis16260/adis16265 pin configuration and fu nction descriptions vref com com vcc vcc 20 19 18 17 16 sclk 1 15 dout 2 top view 14 (not to scale) din 3 13 positive output cs 4 rotational 12 direction dio0 5 dnc = do not connect 11 10 9 876 filt rate aux adc aux dac dnc dio1 rst dnc dnc dnc figure 5. pin configuration table 4. pin function descriptions 06070-004 pin no. mnemonic type 1 description 1 sclk i spi, serial clock. 2 dout o spi, data output. 3 din i spi, data input. 4 cs i spi, chip select, active low. 5, 6 dio0, dio1 i/o multifunction digital input/output pin. 7 rst i reset, active low. this resets the sensor signal conditioning circuit and initiates a start-up sequence. 8, 9, 10, 11 dnc C do not connect. 12 aux dac o auxiliary dac analog output voltage. 13 aux adc i auxiliary adc analog input voltage. 14 rate o analog rate signal output (uncalibrated). 15 filt i analog amplifier summing junction. this is used fo r setting the analog bandwidth. see the analog bandwidth section for more details. 16, 17 vcc s 5.0 v power supply. 18, 19 com s common. reference point for all circuitry in the adis16260/adis16265. 20 vref o precision reference output. 1 s = supply; o = output; i = input. recommended layout 5.0865 8 3.800 8 0.773 16 10.173 7.600 2 4 0.500 20 1.127 20 06070-010 11mm 11mm stacked lga package figure 6. recommended pad layout (units in millimeters) rev. pra | page 7 of 19 adis16260/adis16265 preliminary technical data typical performance characteristics figure 7. root allan variance vs. tau, 320/sec range rev. pra | page 8 of 19 preliminary technical data adis16260/adis16265 theory of operation overview the core angular rate sensor integrated inside the adis16260/ adis16265 is based on the analog devices i mems technology. this sensor operates on the principle of a resonator gyroscope. two polysilicon sensing structures each contain a dither frame electrostatically driven to resonance. this provides the necessary velocity element to produce a coriolis force during rotation. at two of the outer extremes of each frame, orthogonal to the dither motion, are movable fingers placed between fixed fingers to form a capacitive pickoff structure that senses coriolis motion. the resulting signal is fed to a series of gain and demodulation stages that produce the electrical rate signal output. the base sensor output signal is sampled using an adc, and then the digital data is fed into a proprietary digital calibration circuit. this circuit contains calibration coefficients from the factory calibration, along with user-defined calibration registers that can be used to calibrate system-level errors. the calibrated gyroscope data (gyro_out) is made available through output data registers along with temperature, power supply, auxiliary adc, and relative angle output calculations. relative angle estimate the angl_out register offers the integration of the gyro_out data. in order for this information to be useful, the reference angle must be known. this can be accomplished by reading the register contents at the initial time, before starting the monitoring, or by setting its contents to zero. this number is reset to zero when the null command is used, after a reset command is used, and during power-up. this function can be used to estimate change in angle over a period. the user is cautioned to fully understand the stability requirements and the time period over which to use this estimated relative angle position. factory calibration the adis16260/adis16265 provide a factory calibration that includes correction for initial tolerance and power supply variation. in addition, the adis16265 provides correction for temperature variation. this calibration includes individual sensor characterization and custom correction coefficient calculation. auxiliary adc function the auxiliary adc function integrates a standard 12-bit adc into the adis16260/adis16265 to digitize other system-level analog signals. the output of the adc can be monitored through the aux_adc control register, as defined in table 6. the adc is a 12-bit successive approximation converter. the output data is presented in straight binary format with the full- scale range extending from 0 v to 2.5 v. the 2.5 v upper limit is derived from the on-chip precision internal reference. figure 8 shows the equivalent circuit of the analog input structure of the adc. the input capacitor (c1) is typically 4 pf and can be attributed to parasitic package capacitance. the two diodes provide esd protection for the analog input. care must be taken to ensure that the analog input signals never exceed the range of ?0.3 v to +3.5 v. this causes the diodes to become forward-biased and to start conducting. the diodes can handle 10 ma without causing irreversible damage. the resistor is a lumped component that represents the on resistance of the switches. the value of this resistance is typically 100 . capacitor c2 represents the adc sampling capacitor and is typically 16 pf. c2 c1 r1 v dd d d 06070-005 figure 8. equivalent analog input circuit conversion phase: switch open track phase: switch closed for ac applications, it is recommended to remove high frequency components from the analog input signal by using a low-pass filter on the analog input pin. in applications where harmonic distortion and signal-to-noise ratio are critical, the analog input must be driven from a low impedance source. large source impedances significantly affect the ac performance of the adc. this can necessitate the use of an input buffer amplifier. when no input amplifier is used to drive the analog input, the source impedance should be limited to values lower than 1 k. rev. pra | page 9 of 19 adis16260/adis16265 preliminary technical data basic operation the adis16260/adis16265 are designed for simple integration into industrial system designs, requiring only a 5.0 v power supply and a 4-wire, industry standard serial peripheral interface (spi). all outputs and user-programmable functions are handled by a simple register structure. each register is 16 bits in length and has its own unique bit map. the 16 bits in each register consist of an upper (d8 to d15) byte and a lower (d0 to d7) byte, each of which has its own 6-bit address. serial peripheral interface (spi) the adis16260/adis16265 serial per iph eral interface (spi) port includes four signals: chip select ( cs ), seri al clock (sclk), data input (din), and data output (dout). the cs line enables the adis16260/adis16265 spi port and frames each spi event, which consists of single or multiple data frames. when this signal is high, the dout lines are in a high impedance state and the signals on din and sclk have no impact on operation. a complete data frame contains 16 clock cycles. because the spi port operates in full duplex mode, it supports simultaneous, 16-bit receive (din) and transmit (dout) functions during the same data frame. refer to table 2, figure 2, and figure 3 for detailed timing and operation of the spi port. writing to registers figure 9 displays a typical data frame for writing a command to a control register. in this case, the first bit of the din sequence is a 1, followed by a 0, the 6-bit address, and the 8-bit data command. because each write command covers a single byte of data, two data frames are required when writing the entire 16-bit space of a register. reading from registers reading the contents of a register requires a modification to the sequence in figure 9. in this case, the first two bits in the din sequence are 0, followed by the address of the register. each register has two addresses (upper, lower), but either one can be used to access its entire 16 bits of data. the final eight bits of the din sequence are irrelevant and can be counted as dont cares during a read command. during the next data frame, the dout sequence contains the registers 16-bit data, as shown in figure 10. although a single read command requires two separate data frames, the full duplex mode minimizes this overhead, requiring only one extra data frame when continuously sampling. data frame cs scl k w/r a5 a4 a3 a1 a2 a0 dc7 dc6 dc5 dc4 dc3 dc2 dc0 din dc1 write = 1 register address data for write commands read = 0 dont care for read commands figure 9. din bit sequence data frame cs data frame 06070-006 06070-007 address dont care next command sclk din dont care dont care zero w /r bit based on previous command 16-bit register contents dout figure 10. spi sequence for read commands rev. pra | page 10 of 19 preliminary technical data adis16260/adis16265 data output register access the adis16260/adis16265 provide access to calibrated rotation measurements, relative angle estimates, power supply measurements, temperature measurements, and an auxiliary 12-bit adc channel. this output data is continuously updating internally, regardless of user read rates. the following bit map describes the structure of all output data registers, except endurance, in the adis16260/adis16265. table 5. register bit map msb lsb nd ea d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 the msb holds the new data (nd) indicator. when the output registers are updated with new data, the nd bit goes to a 1 state. after the output data is read, it returns to a 0 state. the ea bit is used to indicate a system error or an alarm condition that can result from a number of conditions, such as a power supply that is out of the specified operating range. see the status and diagnostics section for more details. the output data is either 12 bits or 14 bits in length. for all of the 12-bit output data, bit d13 and bit d12 are assigned dont care status. the output data register map is located in table 6 and provides all of the necessary details for accessing each registers data. table 7 displays the output coding for the gyro_out register. figure 11 provides an example spi read cycle for this register. table 6. data output register information name function address resolution (bits) data format scale factor (per lsb) endurance supply_out gyro_out aux_adc temp_out angl_out flash memory write counter power supply data gyroscope data auxiliary analog input data sensor temperature data angle output 0x01, 0x00 0x03, 0x02 0x05, 0x04 0x0b, 0x0a 0x 0d, 0x0c 0x0f, 0x0e 16 12 14 12 12 14 binary binary twos complement binary twos complement binary 1 count 1.8315 mv 0.07326/sec 1 0.6105 mv 0.1453c 0.03663 1 assumes that the scalin g is set to 320/sec. table 7. output coding example, gyro_out 1, 2 rate of rotation binary output hex output decimal 320/sec range 160/sec range 80/sec range 600/sec 320/sec 80/sec 40/sec 0.07326/sec 0/sec ?0.07326/sec ?40/sec ?80/sec ?320/sec ?600/sec 300/sec 160/sec 40/sec 20/sec 0.03663/sec 0/sec ?0.03663/sec ?20/sec ?40/sec ?160/sec ?300/sec 150/sec 80/sec 20/sec 10/sec 0.018315/sec 0/sec ?0.018315/sec ?10/sec ?20/sec ?80/sec ?150/sec 01 1111 1111 1111 01 0001 0001 0000 00 0100 0100 0100 00 0010 0010 0010 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1101 1101 1110 11 1011 1011 1100 10 1110 1111 0000 10 0000 0000 0000 0x1fff 0x1110 0x0444 0x0222 0x0001 0x0000 0x3fff 0x3dde 0x3bbc 0x2ef0 0x2000 8191 4368 1092 546 1 0 ?1 ?546 ?1092 ?4368 ?8192 1 two msbs have been masked off and are not considered in the coding. 2 nominal sensitivity and zero offset null performance are assumed. cs sclk din dout address = 000101 data = 1011 1101 1101 1110 new data, no alarm, gyro_out = C40/second w /r bit = 0 0 6070-008 figure 11. example read cycle, 320/sec setting rev. pra | page 11 of 19 adis16260/adis16265 preliminary technical data programming and control control register overview the adis16260/adis16265 offer many programmable features controlled by writing commands to the appropriate control registers using the spi. table 8 provides a summary of these control registers, which controls the operation of the following parameters: ? calibration ? global commands ? operational control ? sample rate ? power management ? digital filtering ? dynamic range ? dac output ? digital i/o ? operational status and diagnostics ? self-test ? status conditions ? alarms table 8. control register memory map control register structure the adis16260/adis16265 uses a temporary, ram-based memory structure to facilitate the control registers displayed in table 8. the start-up configuration is stored in a flash memory structure that automatically loads into the control registers during the start-up sequence. each nonvolatile register has a corresponding flash memory location, for storing the latest configuration contents. since flash memory has endurance limitations, the contents of each nonvolatile register must be manually stored to flash (note that the contents of the control register contents are only nonvolatile when they are stored to flash). the manual flash update command, made available in the command register, provides this function. the endurance register provides a counter that allows for memory reliability management against the 20,000-write cycle specification. register name type volatility address bytes function reference table gyro_off r/w nonvolatile 0x15, 0x14 2 gyroscop e bias offset factor table 9, table 10 gyro_scale r/w nonvolatile 0x 17, 0x16 0x18 to 0x1f 2 8 gyroscope scale factor reserved table 11, table 12 alm_mag1 r/w nonvolatile 0x21, 0x20 2 alarm 1 ampl itude threshold and polarity table 31, table 32 alm_mag2 r/w nonvolatile 0x23, 0x22 2 alarm 2 ampl itude threshold and polarity table 35, table 36 alm_smpl1 r/w nonvolatile 0x25, 0x24 2 alar m 1 sample period table 33, table 34 alm_smpl2 r/w nonvolatile 0x27, 0x26 2 alar m 2 sample period table 37, table 38 alm_ctrl r/w nonvolatile 0x29, 0x28 0x2a to 0x2f 2 6 alarm control register reserved table 39, table 40 aux_dac r/w volatile 0x31, 0x30 2 auxiliary dac data table 21, table 22 gpio_ctrl r/w volatile 0x33, 0x32 2 auxiliary di gital i/o control register table 23, table 24 msc_ctrl r/w nonvolatile 1 0x35, 0x34 2 miscellaneous control register table 26, table 27 smpl_prd r/w nonvolatile 0x37, 0x36 2 adc sa mple period control table 15, table 16 sens/avg r/w nonvolatile 0x39, 0x38 2 defines the dynamic range (sensitivity setting) and the number of taps for the digital filter table 19, table 20 slp_cnt r/w volatile 0x3b, 0x3a 2 counter used to determine length of power- down mode table 17, table 18 status r volatile 0x3d, 0x3c 2 system status register table 28, table 29 command w n/a 0x3f, 0x3e 2 system command register table 13, table 14 1 the contents of the upper byte are nonvolatile; the contents of the lower byte are volatile. rev. pra | page 12 of 19 preliminary technical data adis16260/adis16265 calibration the adis16260/adis16265 are factory-calibrated for sensitivity and bias. it also provides several user calibration functions for simplifying field-level corrections. the calibration factors are stored in nonvolatile memory and are applied using the following linear calibration equation: y = mx + b where: y is the calibrated output data. x is the precalibration data. m is the sensitivity scale factor. b is the offset scale factor. there are three options for system-level calibrations of the bias in the adis16260/adis16265: auto-null, factory calibration restore, and manual calibration updates. the auto-null and factory reset options are described in the global commands section. optional field-level calibrations use the preceding equation and require two steps: 1. characterize the behavior of the adis16260/adis16265 at predefined critical operating conditions. 2. use this characterization data to calculate and load the contents of gyro_off (b) and gyro_scale (m). the gyro_off provides a calibration range of 37.5/sec, and its contents are nonvolatile. the gyro_scale register provides a calibration range of 0 to 1.9995, and its contents are also nonvolatile. table 9. gyro_off register definition address scale 1 default format access 0x15, 0x14 0.018315/sec 0x0000 twos complement r/w 1 scale is the weight of each lsb. table 10. gyro_off bit descriptions bit description 15:12 not used 11:0 data bits table 11. gyro_scale register definition address scale 1 default 2 format access 0x17, 0x16 0.0487% 0x0800 binary r/w 1 scale is the weight of each lsb. 2 equates to a scale factor of one. table 12. gyro_scale bit descriptions bit description 15:12 not used 11:0 data bits global commands the adis16260/adis16265 provide global commands for common operations such as auto-null, factory calibration restore, manual flash update, auxiliary dac latch, and software reset. each of these global commands has a unique control bit assigned to it in the command register and is initiated by writing a 1 to its assigned bit. the auto-null function does two things: it resets the contents of the angl_out register to zero, and it adjusts the gyro_out register to zero. this automated adjustment takes two steps: 1. read gyro_out. 2. write the opposite of this value into the gryo_off register. sensor noise influences the accuracy of this step. for optimal calibration accuracy, set the number of filtering taps to its maximum, wait for the appropriate number of samples to process through the filter, and then exercise this option. the factory calibration restore command sets the contents of gyro_off to 0x0000 and gyro_scale to 0x0800, erasing any field-level calibration contents. the manual flash update writes the contents of each nonvolatile register into flash memory for storage. this process takes approximately 50 ms and requires the power supply voltage to be within specification for the duration of the event. it is worth noting that this operation also automatically follows the auto-null and factory reset commands. the dac latch command loads the contents of aux_dac into the dac latches. since the aux_dac contents must be updated one byte at a time, this command ensures a stable dac output voltage during updates. finally, the software reset command sends the adis16260/adis16265 digital process or in to a restart sequence, effectively doing the same thing as the rst line. table 13. command register definition address default format access 0x3f, 0x3e n/a n/a write only table 14. command bit descriptions bit description 15:8 not used 7 software reset command 6:4 not used 3 manual flash update command 2 auxiliary dac data latch 1 factory calibration restore command 0 auto-null command rev. pra | page 13 of 19 adis16260/adis16265 operational control internal sample rate the internal sample rate defines how often data output variables are updated, independent of the rate at which they are read out on the spi port. the smpl_prd register controls the adis16260/adis16265 internal sample rate and has two parts: a selectable time base and a multiplier. when smpl_prd is greater than zero, the sample period can be calculated using the following equation: t s = t b ( n s + 1) where: t s is the sample period. t b is the time base. n s is the increment setting. when smpl_prd[7:0] = 0x00, the internal sample setting is 2048sps. since this mode bypasses an internal filtering network, it will result in a total noise increase of approximately 25%. this sens_avg register provides opportunity for noise reduction. the default value is the maximum 256 samples per second, and the contents of this register are nonvolatile. table 15. smpl_prd register definition address default format access 0x37, 0x36 0x0001 n/a r/w table 16. smpl_prd bit descriptions bit description 15:8 not used 7 time base, 0 = 1.953 ms, 1 = 60.54 ms 6:0 multiplier the following is an example calculation of the sample period for the adis16260/adis16265: if smpl_prd = 0x0007, b7 b0 = 00000111 b7 = 0 t b = 1.953 ms b6 b0 = 000000111 n s = 7 t s = t b (n s + 1) = 1.953 ms (7 + 1) = 15.624 ms f s = 1M t s = 64 sps the sample rate setting has a direct impact on the spi data rate capability. for sample rates of 64 sps and above, the spi sclk can run at a rate up to 2.5 mhz. for sample rates below 64 sps, the spi sclk can run at a rate up to 1 mhz. the sample rate setting also affects the power dissipation. when the sample rate is set below 64 sps, the power dissipation reduces by a factor of 60%. the two different modes of operation offer a system-level trade-off between performance (sample rate, serial transfer rate) and power dissipation. power management in addition to offering two different performance modes for power optimization, the adis16260/adis16265 offer a programmable shutdown period. writing the appropriate sleep time to the slp_cnt register shuts the device down for the specified time. the following example provides an illustration of this relationship: b7 b0 = 00000110 sleep period = 3 sec after completing the sleep period, the adis16260/adis16265 return to normal operation. if measurements are required before sleep period completi on, the adis16260/adis16265 can be awakened by p utting the cs line in a zero logic state. otherwise, the cs line must be kept high to maintain sleep mode. table 17. slp_cnt register definition address scale 1 default format access 0x3b, 0x3a 0.5 sec 0x0000 binary r/w 1 scale is the weight of each lsb. table 18. slp_cnt bit descriptions bit description 15:8 not used 7:0 data bits analog bandwidth the analog bandwidth of the adis16260/adis16265 is 50 hz. this bandwidth can be reduced by placing an external capacitor across the rate and filt pins. in this case, the analog bandwidth can be calculated using the following equation: f out = 1/(2 r out ( c out + c in )) where: r out = 90 k. c out is the external capacitance. cin = 0.0377f when sens_avg[7] = 0 cin = 0.0047f when sens_avg[7] = 1 digital filtering the adis16260/adis16265 gyro_out signal path has a nominal analog bandwidth of 50 hz. the adis16260 provides a bartlett window fir filter for additional noise reduction on all of the output data registers. the sens/avg register stores the number of taps in this filter in seven power-of-two step sizes (that is, 2 m = 1, 2, 4, 16, 32, 64, and 128). filter setup requires one simple step: write the appropriate m factor to the assigned bits in the sens/avg register. the bit assignments are listed in table 20. the following equation offers a frequency response relationship for this filter: 2 sin( n f t s ) h ( f ) = h ( f ) ? h ( f ) = b a a n sin( f t s ) rev. pra | page 14 of 19 7 preliminary technical data adis16260/adis16265 are volatile, which means that the desired output level must be set after every reset and power cycle event. 0 C160 C140 C120 C100 C80 C60 C40 C20 magnitude (db) n = 128 n = 16 n = 2 n = 4 table 21. aux_dac register definition address default format access 0x31, 0x30 0x0000 binary r/w table 22. aux_dac bit descriptions bit description 15:12 not used 11:0 data bits 0.001 0.01 0.1 1 frequency (f/fs) 06070-009 general-purpose i/o figure 12. bartlett window fir frequency response dynamic range the adis16260/adis16265 provide three dynamic range settings: 80/sec, 160/sec, and 320/sec. the lower dynamic range settings (80, 160) limit the minimum filter tap sizes in order to maintain the resolution as the maximum rate measurements decrease. the recommended order for program- ming the sens/avg register is (1) dynamic range and then (2) filtering response. the contents of the sens/avg register are nonvolatile. table 19. sens/avg register definition the adis16260/adis16265 provide two general-purpose pins that enable digital i/o control using the spi. the gpio_ctrl control register establishes the configuration of these pins and handles the spi-to-pin controls. each pin provides the flexibility of both input (read) and output (write) operations. for example, writing a 0x0202 to this register establishes line 0 as an output and sets its level as a one. writing 0x0000 to this register establishes both lines as inputs, and their status can be read through bit 0 and bit 1 of this register. the digital i/o lines are also available for data-ready and alarm/error indications. in the event of conflict, the following priority structure governs the digital i/o configuration: address default format access 0x39, 0x38 0x0402 binary r/w table 20. sens/avg bit descriptions bit value description 1. msc_ctrl 2. alm_ctrl 3. gpio_ctrl 15:11 not used 10:8 sensitivity selection bits 100 320/sec (default condition) 010 160/sec, filter taps 4 (bits[3:0] 0x02) table 23. gpio_ctrl register definition address default format access 0x33, 0x32 0x0000 n/a r/w 001 80/sec, filter taps 16 (bits[3:0] 0x04) table 24. gpio_ctrl bit descriptions bit sensor bandwidth selection: 1 = 300hz, 0 = 50hz 15:10 9 6:4 not used 3:0 filter tap setting, m = binary number (number of taps, n = 2 m ) 8 auxiliary dac the auxiliary dac provides a 12-bit level adjustment function. 7:2 the aux_dac register controls the operation of this feature. it 1 offers a rail-to-rail buffered output that has a range of 0 v to 2.5 v. the dac can drive its output to within 5 mv of the ground reference when it is not sinking current. as the output approaches 0 ground, the linearity begins to degrade (100 lsb beginning point). as the sink current increases, the nonlinear range increases. the dac output latch function, contained in the command register, provides continuous operation while writing each byte of this register. the contents of this register description not used general-purpose i/o line 1 polarity 1 = high 0 = low general-purpose i/o line 0 polarity 1 = high 0 = low not used general-purpose i/o line 1, data direction control 1 = output 0 = input general-purpose i/o line 0, data direction control 1 = output 0 = input rev. pra | page 15 of 19 adis16260/adis16265 status and diagnostics the adis16260/adis16265 provide a number of status and diagnostic functions. table 25 provides a summary of these functions, along with their appropriate control registers. table 25. status and diagnostic functions function register data-ready i/o indicator msc_ctrl self-test, mechanical check for mems sensor msc_ctrl status, check for predefined error conditions status flash memory endurance endurance alarms, configure and check for user-specific conditions alm_mag1/2 alm_smpl1/2 alm_ctrl data-ready i/o indicator the data-ready function provides an indication of updated output data. the msc_ctrl register provides the opportunity to configure either of the general-purpose i/o pins (dio0 and dio1) as a data-ready indicator signal. after each output register update, the digital i/o changes states, then returns to its original state, creating a pulsed waveform. the duty cycle of that waveform is in between 15% and 35%. table 26. msc_ctrl register definition address default format access 0x35, 0x34 0x0000 n/a r/w table 27. msc_ctrl bit descriptions bit 15:11 10 9 8 7:3 2 1 0 description not used internal self-test enable 1 = enabled 0 = disabled external negative rota tion self-test enable 1 = enabled 0 = disabled external positive rota tion self-test enable 1 = enabled 0 = disabled not used data-ready enable 1 = enabled 0 = disabled data-ready polarity 1 = active high 0 = active low data-ready line select 1 = dio1 0 = dio0 self-test the msc_ctrl register also provides a self-test function, which verifies the mems sensors mechanical integrity. there are two different self-test options: (1) internal self-test and (2) external self-test. the internal test provides a simple, two-step process for checking the mems sensor: (1) start the process by writing a 1 to bit 10 in the msc_ctrl register and (2) check the result by reading bit 5 of the status register, after 35 ms. the external self-test is a static condition that can be enabled and disabled. in this test, both positive and negative mems sensor movements are available. after writing to the appropriate control bit, the gyro_out register reflects the changes after a delay that reflects the sensor signal chain response time. for example, the standard 52 hz bandwidth reflects an exponential response with a time constant of 3.2 ms. if the bandwidth is reduced externally (capacitor across rate and filt) or internally (increasing the number of filter taps, sens/avg), this time constant increases. for the internal self-test option, increasing the delay can produce false alarms, since the internal timing for this function is optimized for maximum bandwidth. the appropriate bit definitions for self-test are listed in table 26 and table 27. status conditions the status register contains the following error-condition flags: alarm conditions, self-test status, angular rate over range, spi communication failure, control register update failure, and power supply out of range. see table 28 and table 29 for the appropriate register access and bit assignment for each flag. the bits assigned for checking power supply range and angular rate over range automatically reset to 0 when the error condition no longer exists. the remaining error-flag bits in the status register require a read in order to return them to 0. note that a status register read clears all of the bits to 0. table 28. status register definition address default format access 0x3d, 0x3c 0x0000 n/a read-only table 29. status bit descriptions bit description 15:10 not used 9 alarm 2 status 1 = active, 0 = inactive 8 alarm 1 status 1 = active, 0 = inactive 7:6 not used 5 self-test diagnostic error flag 1 = error condition, 0 = normal operation 4 angular rate over range 1 = error condition, 0 = normal operation 3 spi communications failure 1 = error condition, 0 = normal operation 2 control register update failed 1 = error condition, 0 = normal operation 1 power supply above 5.25 v 1 = above 5.25 v, 0 = below 5.25 v (normal) 0 power supply below 4.75 v 1 = below 4.75 v, 0 = above 4.75 v (normal) rev. pra | page 16 of 19 preliminary technical data adis16260/adis16265 flash memory endurance the endurance register maintains a running count of writes to the flash memory. it provides up to 32,768 counts. note that if this count is exceeded, the register wraps around, and goes back to zero, before beginning to increment again. table 30. endurance register definition address default format access 0x01, 0x00 n/a binary read-only alarms the adis16260/adis16265 provide two independent alarm options for event detection. event detections occur when output register data meets the configured conditions. configuration options are: ? all output data registers are available for monitoring as the source data. ? the source data can be filtered or unfiltered. ? comparisons can be static or dynamic (rate of change). ? the threshold levels and times are configurable. ? comparison can be greater than or less than. the alm_mag1 register and the alm_mag2 register both establish the threshold level for detecting events. they take on the format of the source data and provide a bit for establishing the greater than/less than comparison direction. when making dynamic comparisons, the alm_smpl1 register and the alm_smpl2 register establish the number of averages taken for the source data as a reference for comparison. in this configuration, each subsequent source data sample is subtracted from the previous one, establishing an instantaneous delta. the alm_ctrl register controls the source data selection, static/dynamic selection, filtering selection, and digital i/o usage for the alarms. the rate of change calculation is y c = 1 n ds y ( n + 1) ? y ( n ) n ds n = 1 rate of change alarm ? is y c > or < m c ? where: n ds is the number of samples in alm_smpl1/2. y(n) is the sampled output data. m c is the magnitude for comparison in alm_mag1/2. y c is the factor to be compared with m c . > or < is determined by the msb in alm_mag1/2. table 31. alm_mag1 register definition address default format access 0x21, 0x20 0x0000 n/a r/w table 32. alm_mag1 bit descriptions bit description 15 comparison polarity: 1 = greater than, 0 = less than 14 not used 13:0 data bits: format matches source data format table 33. alm_smpl1 register definition address default format access 0x25, 0x24 0x0000 binary r/w table 34. alm_smpl1 bit descriptions bit description 15:8 not used 7:0 data bits table 35. alm_mag2 register definition address default format access 0x23, 0x22 0x0000 n/a r/w table 36. alm_mag2 bit descriptions bit 15 14 13:0 description comparison polarity 1 = greater than 0 = less than not used data bits: format matches source data format table 37. alm_smpl2 register definition address default format access 0x27, 0x26 0x0000 binary r/w table 38. alm_smpl2 bit designations bit description 15:8 not used 7:0 data bits table 39. alm_ctrl register definition address default format access 0x29, 0x28 0x0000 n/a r/w rev. pra | page 17 of 19 adis16260/adis16265 table 40. alm_ctrl bit descriptions bit value description 15 rate of change (roc) enable for alarm 2 1 = rate of change 0 = static level 14:12 alarm 2 source selection 000 disable 001 power supply output 010 gyroscope output 011 inactive 100 inactive 101 auxiliary adc output 110 temperature sensor output 111 inactive 11 rate of change (roc) enable for alarm 1 1 = rate of change 0 = static level 10:8 alarm 1 source selection 000 disable 001 power supply output 010 gyroscope output 011 inactive 100 inactive 101 auxiliary adc output 110 temperature sensor output 111 inactive 7:5 not used 4 filtered data comparison 1 = filtered data 0 = unfiltered data 3 not used 2 alarm output enable 1 = enabled 0 = disabled 1 alarm output polarity 1 = active high 0 = active low 0 alarm output line select 1 = dio1 0 = dio0 rev. pra | page 18 of 19 preliminary technical data adis16260/adis16265 outline dimensions top view bottom view pin 1 indicator 1.000 bsc (20 ) 11.00 typ 1 5 6 10 11 15 16 20 11.15 max 7.600 bsc (4 ) 3.800 bsc (8 ) 10.173 bsc (2 ) 0.200 min 0.900 bsc (16 ) 0.373 bsc (20 ) (all sides ) 5.50 max 7.00 typ side view 022007-b figure 13. 20-terminal stacked land grid array [lga] (cc-20-1) dimensions shown in millimeters ordering guide model temperature range package description package option ADIS16260ACCZ 1 adis16265accz 1 adis16260/pcbz 1 adis16265/pcbz 1 ?40c to +85c ?40c to +85c 20-terminal stacke d land grid array [lga] 20-terminal stacke d land grid array [lga] evaluation board for the adis16260 evaluation board for the adis16265 cc-20-1 cc-20-1 1 z = rohs compliant part. ?2006C2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. pr08246-0-5/09(pra) rev. pra | page 19 of 19 |
Price & Availability of ADIS16260ACCZ
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |